The present disclosure relates to a voltage conversion circuit and an electronic circuit. More specifically, the present disclosure relates to a voltage conversion circuit and an electronic circuit for voltage conversion causing a delay time.
In the past, semiconductor integrated circuits such as LSI (Large Scale Integration) have been managed in many cases by being divided into a plurality of regions (hereinafter, referred to as “power-supply domains”) with different power-supply voltages in order to efficiently use power. In such semiconductor integrated circuits, a level converter that converts the voltage of a signal is provided between the power-supply domains in order to propagate the signal accurately. The level converter includes a plurality of logic inversion elements such as inverters. Those logic inversion elements may have differences in delay time between a rising edge and a falling edge. So, there is a risk that a period of time from the rising edge to the falling edge of the signal with the changed voltage varies as compared to the case before the conversion. Such a variation is desirably small in terms of preventing malfunction of the circuit.
In this regard, in order to reduce the variation in the period of time from the rising edge to the falling edge, a level shifter is proposed which includes two voltage shifter circuits connected to an input-side circuit in parallel (see, for example, Japanese Patent Application Laid-open No. 2012-105277). Those two voltage shifter circuits convert voltages of input clock signals and generate output clock signals having different delay times of the rising edge and the falling edge. Those voltage shifter circuits have respective output terminals connected to an output-side circuit in common and output a clock signal of a logical value of a so-called wired OR (logical sum).